summaryrefslogtreecommitdiff
path: root/implementations/vhdl/Decrypt/lilliputtbcii256v1
diff options
context:
space:
mode:
Diffstat (limited to 'implementations/vhdl/Decrypt/lilliputtbcii256v1')
-rw-r--r--implementations/vhdl/Decrypt/lilliputtbcii256v1/chiffrement.vhd129
-rw-r--r--implementations/vhdl/Decrypt/lilliputtbcii256v1/const_pack.vhd17
-rw-r--r--implementations/vhdl/Decrypt/lilliputtbcii256v1/crypt_pack.vhd47
-rw-r--r--implementations/vhdl/Decrypt/lilliputtbcii256v1/inner_sbox_a.vhd42
-rw-r--r--implementations/vhdl/Decrypt/lilliputtbcii256v1/inner_sbox_b.vhd41
-rw-r--r--implementations/vhdl/Decrypt/lilliputtbcii256v1/inner_sbox_c.vhd43
-rw-r--r--implementations/vhdl/Decrypt/lilliputtbcii256v1/inv_multiplication.vhd130
-rw-r--r--implementations/vhdl/Decrypt/lilliputtbcii256v1/key_schedule.vhd101
-rw-r--r--implementations/vhdl/Decrypt/lilliputtbcii256v1/machine_etat_chiffrement.vhd145
-rw-r--r--implementations/vhdl/Decrypt/lilliputtbcii256v1/multiplications.vhd132
-rw-r--r--implementations/vhdl/Decrypt/lilliputtbcii256v1/roundexe_liliput.vhd143
-rw-r--r--implementations/vhdl/Decrypt/lilliputtbcii256v1/sbox.vhd82
-rw-r--r--implementations/vhdl/Decrypt/lilliputtbcii256v1/state_key_register.vhd26
-rw-r--r--implementations/vhdl/Decrypt/lilliputtbcii256v1/state_register.vhd30
-rw-r--r--implementations/vhdl/Decrypt/lilliputtbcii256v1/tb/top_tb.vhd95
-rw-r--r--implementations/vhdl/Decrypt/lilliputtbcii256v1/top.vhd102
16 files changed, 1305 insertions, 0 deletions
diff --git a/implementations/vhdl/Decrypt/lilliputtbcii256v1/chiffrement.vhd b/implementations/vhdl/Decrypt/lilliputtbcii256v1/chiffrement.vhd
new file mode 100644
index 0000000..567f0f1
--- /dev/null
+++ b/implementations/vhdl/Decrypt/lilliputtbcii256v1/chiffrement.vhd
@@ -0,0 +1,129 @@
+library IEEE;
+library work;
+use IEEE.numeric_std.ALL;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.crypt_pack.ALL;
+
+entity chiffrement is port (
+
+chiffrement_i : in type_state;
+permutation_i : in std_logic;
+round_key_i : in type_key;
+chiffrement_o : out type_state;
+data_out_valid_i : in std_logic;
+data_o : out bit128);
+
+end chiffrement;
+
+architecture chiffrement_arch of chiffrement is
+
+signal non_linear_s : type_state;
+signal non_linear_s1 : type_state;
+signal linear_s : type_state;
+signal chiffrement_s : type_state;
+signal permut_s : type_state;
+
+component sbox
+ port (
+ sbox_i : in bit8;
+ sbox_o : out bit8
+ );
+end component;
+
+
+begin
+
+chiffrement_s <= chiffrement_i;
+
+
+non_linear_s1(0)(0)<= chiffrement_i(0)(0);
+non_linear_s1(0)(1)<= chiffrement_i(0)(1);
+non_linear_s1(0)(2)<= chiffrement_i(0)(2);
+non_linear_s1(0)(3)<= chiffrement_i(0)(3);
+non_linear_s1(1)(0)<= chiffrement_i(1)(0);
+non_linear_s1(1)(1)<= chiffrement_i(1)(1);
+non_linear_s1(1)(2)<= chiffrement_i(1)(2);
+non_linear_s1(1)(3)<= chiffrement_i(1)(3);
+non_linear_s(2)(0)<= chiffrement_i(1)(3) xor round_key_i(1)(3);
+non_linear_s(2)(1)<= chiffrement_i(1)(2) xor round_key_i(1)(2);
+non_linear_s(2)(2)<= chiffrement_i(1)(1) xor round_key_i(1)(1);
+non_linear_s(2)(3)<= chiffrement_i(1)(0) xor round_key_i(1)(0);
+non_linear_s(3)(0)<= chiffrement_i(0)(3) xor round_key_i(0)(3);
+non_linear_s(3)(1)<= chiffrement_i(0)(2) xor round_key_i(0)(2);
+non_linear_s(3)(2)<= chiffrement_i(0)(1) xor round_key_i(0)(1);
+non_linear_s(3)(3)<= chiffrement_i(0)(0) xor round_key_i(0)(0);
+
+
+boucle_ligne : for i in 2 to 3 generate
+ boucle_colonne : for j in 0 to 3 generate
+ sboxx: sbox port map(
+ sbox_i => non_linear_s(i)(j),
+ sbox_o => non_linear_s1(i)(j)
+ );
+ end generate;
+ end generate;
+
+linear_s(0)(0)<= non_linear_s1(0)(0);
+linear_s(0)(1)<= non_linear_s1(0)(1);
+linear_s(0)(2)<= non_linear_s1(0)(2);
+linear_s(0)(3)<= non_linear_s1(0)(3);
+linear_s(1)(0)<= non_linear_s1(1)(0);
+linear_s(1)(1)<= non_linear_s1(1)(1);
+linear_s(1)(2)<= non_linear_s1(1)(2);
+linear_s(1)(3)<= non_linear_s1(1)(3);
+linear_s(2)(0)<= non_linear_s1(2)(0) xor chiffrement_s(2)(0);
+linear_s(2)(1)<= non_linear_s1(2)(1) xor chiffrement_s(2)(1) xor chiffrement_s(1)(3);
+linear_s(2)(2)<= non_linear_s1(2)(2) xor chiffrement_s(2)(2) xor chiffrement_s(1)(3);
+linear_s(2)(3)<= non_linear_s1(2)(3) xor chiffrement_s(2)(3) xor chiffrement_s(1)(3);
+linear_s(3)(0)<= non_linear_s1(3)(0) xor chiffrement_s(3)(0) xor chiffrement_s(1)(3);
+linear_s(3)(1)<= non_linear_s1(3)(1) xor chiffrement_s(3)(1) xor chiffrement_s(1)(3);
+linear_s(3)(2)<= non_linear_s1(3)(2) xor chiffrement_s(3)(2) xor chiffrement_s(1)(3);
+linear_s(3)(3)<= non_linear_s1(3)(3) xor chiffrement_s(3)(3) xor non_linear_s1(0)(1) xor non_linear_s1(0)(2) xor non_linear_s1(0)(3) xor non_linear_s1(1)(0) xor non_linear_s1(1)(1) xor non_linear_s1(1)(2) xor non_linear_s1(1)(3) ;
+
+
+permut_s(0)(0)<= linear_s(3)(1) when permutation_i='1' else linear_s(0)(0);
+permut_s(0)(1)<= linear_s(2)(1) when permutation_i='1' else linear_s(0)(1);
+permut_s(0)(2)<= linear_s(3)(2) when permutation_i='1' else linear_s(0)(2);
+permut_s(0)(3)<= linear_s(2)(0) when permutation_i='1' else linear_s(0)(3);
+permut_s(1)(0)<= linear_s(2)(2) when permutation_i='1' else linear_s(1)(0);
+permut_s(1)(1)<= linear_s(2)(3) when permutation_i='1' else linear_s(1)(1);
+permut_s(1)(2)<= linear_s(3)(0) when permutation_i='1' else linear_s(1)(2);
+permut_s(1)(3)<= linear_s(3)(3) when permutation_i='1' else linear_s(1)(3);
+permut_s(2)(0)<= linear_s(1)(0) when permutation_i='1' else linear_s(2)(0);
+permut_s(2)(1)<= linear_s(1)(1) when permutation_i='1' else linear_s(2)(1);
+permut_s(2)(2)<= linear_s(0)(3) when permutation_i='1' else linear_s(2)(2);
+permut_s(2)(3)<= linear_s(0)(1) when permutation_i='1' else linear_s(2)(3);
+permut_s(3)(0)<= linear_s(0)(2) when permutation_i='1' else linear_s(3)(0);
+permut_s(3)(1)<= linear_s(1)(2) when permutation_i='1' else linear_s(3)(1);
+permut_s(3)(2)<= linear_s(0)(0) when permutation_i='1' else linear_s(3)(2);
+permut_s(3)(3)<= linear_s(1)(3) when permutation_i='1' else linear_s(3)(3);
+
+
+
+
+--toute à la fin
+ row: for i in 0 to 3 generate --On considère uniquement les colonnes
+ col: for j in 0 to 3 generate
+ chiffrement_o(i)(j)<= permut_s(i)(j);-- when permutation_i='1' else X"0";
+ end generate;
+ end generate;
+
+ row1: for i in 0 to 3 generate --On considère uniquement les colonnes
+ col1: for j in 0 to 3 generate
+ --data_o(63-(4*(4*i+j)) downto (60-4*(4*i+j))) <= permut_s(i)(j) when data_out_valid_i = '1' else X"0"; --on vérifie si data_out_valid est égale à 1 dans ce cas on convertie le type_state en bit 128 poour le faire sortir en data_o
+ data_o(7+(8*(4*i+j)) downto (8*(4*i+j))) <= permut_s(i)(j) when data_out_valid_i = '1' else X"00"; --on vérifie si data_out_valid est égale à 1 dans ce cas on convertie le type_state en bit 128 poour le faire sortir en data_o
+ end generate;
+ end generate;
+end chiffrement_arch;
+
+configuration chiffrement_conf of chiffrement is
+ for chiffrement_arch
+ for boucle_ligne
+ for boucle_colonne
+ for all : sbox
+ use entity work.sbox( sbox_arch );
+ end for;
+ end for;
+ end for;
+ end for;
+end configuration chiffrement_conf ;
diff --git a/implementations/vhdl/Decrypt/lilliputtbcii256v1/const_pack.vhd b/implementations/vhdl/Decrypt/lilliputtbcii256v1/const_pack.vhd
new file mode 100644
index 0000000..774e01b
--- /dev/null
+++ b/implementations/vhdl/Decrypt/lilliputtbcii256v1/const_pack.vhd
@@ -0,0 +1,17 @@
+library IEEE;
+library work;
+use IEEE.STD_LOGIC_1164.ALL;
+
+
+package const_pack is
+ constant ROUND_NB : integer;
+ constant TWEAK_LEN : integer;
+ constant KEY_LEN : integer;
+end const_pack;
+
+
+package body const_pack is
+ constant ROUND_NB : integer := 42;
+ constant TWEAK_LEN : integer := 128;
+ constant KEY_LEN : integer := 256;
+end const_pack; \ No newline at end of file
diff --git a/implementations/vhdl/Decrypt/lilliputtbcii256v1/crypt_pack.vhd b/implementations/vhdl/Decrypt/lilliputtbcii256v1/crypt_pack.vhd
new file mode 100644
index 0000000..15f1a17
--- /dev/null
+++ b/implementations/vhdl/Decrypt/lilliputtbcii256v1/crypt_pack.vhd
@@ -0,0 +1,47 @@
+library IEEE;
+library work;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.const_pack.ALL;
+
+package crypt_pack is
+
+ subtype bit2 is std_logic_vector(1 downto 0);
+ subtype bit4 is std_logic_vector(3 downto 0);
+ subtype bit8 is std_logic_vector(7 downto 0);
+ subtype bit16 is std_logic_vector(15 downto 0);
+ subtype bit32 is std_logic_vector(31 downto 0);
+ subtype bit64 is std_logic_vector(63 downto 0);
+ subtype bit128 is std_logic_vector(127 downto 0);
+ subtype bit256 is std_logic_vector(255 downto 0);
+ subtype bit192 is std_logic_vector(191 downto 0);
+ subtype bit80 is std_logic_vector(79 downto 0);
+ subtype bit_tweak is std_logic_vector(TWEAK_LEN-1 downto 0);
+ subtype bit_key is std_logic_vector(KEY_LEN-1 downto 0);
+ subtype bit_tweak_key is std_logic_vector((TWEAK_LEN+KEY_LEN)-1 downto 0);
+
+
+ type row_state is array(0 to 3) of bit8;
+ type type_state is array(0 to 3) of row_state;
+
+ type key_row_state is array(0 to 3) of bit8; --nombre d'element par ligne
+ type type_key is array(0 to 1) of key_row_state; --nombre de ligne
+
+ type type_tweak_key_row is array(0 to 7) of bit8;
+ type type_tweak_key_array is array(0 to ((TWEAK_LEN+KEY_LEN)/64)-1) of type_tweak_key_row;
+
+ type keyschedule_row_state is array(0 to 3) of bit8; -- to 4 pour une matrice bit4
+ type type_keyschedule is array(0 to 3) of keyschedule_row_state;
+
+ constant ROUND : integer;
+ constant TWEAK_KEY_LEN : integer;
+ constant LANE_NB : integer;
+
+
+end crypt_pack;
+
+package body crypt_pack is
+ constant ROUND : integer := ROUND_NB-2; -- round number - 1
+ constant TWEAK_KEY_LEN : integer := TWEAK_LEN+KEY_LEN-1; -- tweak key lenght - 1
+ constant LANE_NB : integer := ((TWEAK_LEN+KEY_LEN)/64); --nuber of lane
+end crypt_pack;
+ \ No newline at end of file
diff --git a/implementations/vhdl/Decrypt/lilliputtbcii256v1/inner_sbox_a.vhd b/implementations/vhdl/Decrypt/lilliputtbcii256v1/inner_sbox_a.vhd
new file mode 100644
index 0000000..18185a1
--- /dev/null
+++ b/implementations/vhdl/Decrypt/lilliputtbcii256v1/inner_sbox_a.vhd
@@ -0,0 +1,42 @@
+library IEEE;
+library work;
+use IEEE.std_logic_1164.all;
+
+entity inner_sbox_a is
+ port(
+ sbox_i : in std_logic_vector(3 downto 0);
+ sbox_o : out std_logic_vector(3 downto 0)
+ );
+end inner_sbox_a;
+
+
+architecture inner_sbox_a_arch of inner_sbox_a is
+
+signal a,b,c,d,x,y,z,t :std_logic;
+signal a1,b1,c1,d1,e :std_logic;
+
+begin
+
+a <= sbox_i(3);
+b <= sbox_i(2);
+c <= sbox_i(1);
+d <= sbox_i(0);
+
+a1 <= e xor a;
+b1 <= b xor c1;
+c1 <= a xor c;
+d1 <= d xor (b and c);
+e <= b xor d1;
+
+x <= c1 and e;
+y <= a and d1;
+z <= e;
+t <= a1 and b1;
+
+sbox_o(3) <= x;
+sbox_o(2) <= y;
+sbox_o(1) <= z;
+sbox_o(0) <= t;
+
+end;
+
diff --git a/implementations/vhdl/Decrypt/lilliputtbcii256v1/inner_sbox_b.vhd b/implementations/vhdl/Decrypt/lilliputtbcii256v1/inner_sbox_b.vhd
new file mode 100644
index 0000000..46f757e
--- /dev/null
+++ b/implementations/vhdl/Decrypt/lilliputtbcii256v1/inner_sbox_b.vhd
@@ -0,0 +1,41 @@
+library IEEE;
+library work;
+use IEEE.std_logic_1164.all;
+
+entity inner_sbox_b is
+ port(
+ sbox_i : in std_logic_vector(3 downto 0);
+ sbox_o : out std_logic_vector(3 downto 0)
+ );
+end inner_sbox_b;
+
+
+architecture inner_sbox_b_arch of inner_sbox_b is
+
+signal a,b,c,d,x,y,z,t :std_logic;
+signal c1,d1 :std_logic;
+
+begin
+
+a <= sbox_i(3);
+b <= sbox_i(2);
+c <= sbox_i(1);
+d <= sbox_i(0);
+
+
+c1 <= c xor (a and d);
+d1 <= b xor (d and c);
+
+
+x <= d xor (a and d1);
+y <= d1;
+z <= a xor (c1 and d1);
+t <= c1;
+
+sbox_o(3) <= x;
+sbox_o(2) <= y;
+sbox_o(1) <= z;
+sbox_o(0) <= t;
+
+end;
+
diff --git a/implementations/vhdl/Decrypt/lilliputtbcii256v1/inner_sbox_c.vhd b/implementations/vhdl/Decrypt/lilliputtbcii256v1/inner_sbox_c.vhd
new file mode 100644
index 0000000..a794485
--- /dev/null
+++ b/implementations/vhdl/Decrypt/lilliputtbcii256v1/inner_sbox_c.vhd
@@ -0,0 +1,43 @@
+library IEEE;
+library work;
+use IEEE.std_logic_1164.all;
+
+
+entity inner_sbox_c is
+ port(
+ sbox_i : in std_logic_vector(3 downto 0);
+ sbox_o : out std_logic_vector(3 downto 0)
+ );
+end inner_sbox_c;
+
+
+architecture inner_sbox_c_arch of inner_sbox_c is
+
+signal a,b,c,d,x,y,z,t :std_logic;
+signal a1,b1,c1,d1,e :std_logic;
+
+begin
+
+a <= sbox_i(3);
+b <= sbox_i(2);
+c <= sbox_i(1);
+d <= sbox_i(0);
+
+a1 <= e xor a;
+b1 <= b xor c1;
+c1 <= a xor c;
+d1 <= not (d xor (b and c));
+e <= b xor d1;
+
+x <= c1 and e;
+y <= a and d1;
+z <= e;
+t <= a1 and b1;
+
+sbox_o(3) <= x;
+sbox_o(2) <= y;
+sbox_o(1) <= z;
+sbox_o(0) <= t;
+
+end;
+
diff --git a/implementations/vhdl/Decrypt/lilliputtbcii256v1/inv_multiplication.vhd b/implementations/vhdl/Decrypt/lilliputtbcii256v1/inv_multiplication.vhd
new file mode 100644
index 0000000..b975b0c
--- /dev/null
+++ b/implementations/vhdl/Decrypt/lilliputtbcii256v1/inv_multiplication.vhd
@@ -0,0 +1,130 @@
+library IEEE;
+library work;
+use IEEE.numeric_std.ALL;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.crypt_pack.ALL;
+
+
+entity inv_multiplication is
+Port (
+ mularray_i : in type_tweak_key_array;
+ mularray_o : out type_tweak_key_array
+ );
+end inv_multiplication;
+
+architecture inv_multiplication_arch of inv_multiplication is
+
+signal x2_M_1 : bit8;
+signal x2_M_3 : bit8;
+signal x2_M_4 : bit8;
+signal x3_M_1 : bit8;
+signal x3_M_3 : bit8;
+signal x3_M_4 : bit8;
+signal x3_M2_1 : bit8;
+signal x3_M2_3 : bit8;
+signal x3_M2_4 : bit8;
+signal x5_MR_3 : bit8;
+signal x5_MR_5 : bit8;
+signal x5_MR_6 : bit8;
+signal x6_MR_3 : bit8;
+signal x6_MR_5 : bit8;
+signal x6_MR_6 : bit8;
+signal x6_MR2_3: bit8;
+signal x6_MR2_5: bit8;
+signal x6_MR2_6: bit8;
+
+begin
+
+mularray_o(0)(7) <= mularray_i(0)(7);
+mularray_o(0)(6) <= mularray_i(0)(6);
+mularray_o(0)(5) <= mularray_i(0)(5);
+mularray_o(0)(4) <= mularray_i(0)(4);
+mularray_o(0)(3) <= mularray_i(0)(3);
+mularray_o(0)(2) <= mularray_i(0)(2);
+mularray_o(0)(1) <= mularray_i(0)(1);
+mularray_o(0)(0) <= mularray_i(0)(0);
+
+mularray_o(1)(7) <= mularray_i(1)(0);
+mularray_o(1)(6) <= mularray_i(1)(7);
+mularray_o(1)(5) <= mularray_i(1)(6);
+mularray_o(1)(4) <= mularray_i(1)(5)xor std_logic_vector(shift_left(unsigned(mularray_i(1)(6)) , 3));
+mularray_o(1)(3) <= mularray_i(1)(4)xor std_logic_vector(shift_right(unsigned(mularray_i(1)(5)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(1)(6)) , 3))) , 3));
+mularray_o(1)(2) <= mularray_i(1)(3);
+mularray_o(1)(1) <= mularray_i(1)(2) xor std_logic_vector(shift_left(unsigned(mularray_i(1)(7)) , 2));
+mularray_o(1)(0) <= mularray_i(1)(1);
+
+x2_M_4 <= mularray_i(2)(5)xor std_logic_vector(shift_left(unsigned(mularray_i(2)(6)) , 3));
+x2_M_3 <= mularray_i(2)(4)xor std_logic_vector(shift_right(unsigned(mularray_i(2)(5)) , 3))xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(2)(6)) , 3))) , 3));
+x2_M_1 <= mularray_i(2)(2) xor std_logic_vector(shift_left(unsigned(mularray_i(2)(7)) , 2));
+
+mularray_o(2)(7) <= mularray_i(2)(1);
+mularray_o(2)(6) <= mularray_i(2)(0);
+mularray_o(2)(5) <= mularray_i(2)(7);
+mularray_o(2)(4) <= mularray_i(2)(6)xor std_logic_vector(shift_left(unsigned(mularray_i(2)(7)) , 3));
+mularray_o(2)(3) <= x2_M_4 xor std_logic_vector(shift_right(unsigned(mularray_i(2)(6)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(2)(7)) , 3))) , 3));
+mularray_o(2)(2) <= x2_M_3;
+mularray_o(2)(1) <= mularray_i(2)(3) xor std_logic_vector(shift_left(unsigned(mularray_i(2)(0)) , 2));
+mularray_o(2)(0) <= x2_M_1;
+
+x3_M_4 <= mularray_i(3)(5)xor std_logic_vector(shift_left(unsigned(mularray_i(3)(6)) , 3));
+x3_M_3 <= mularray_i(3)(4)xor std_logic_vector(shift_right(unsigned(mularray_i(3)(5)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(3)(6)) , 3))) , 3));
+x3_M_1 <= mularray_i(3)(2) xor std_logic_vector(shift_left(unsigned(mularray_i(3)(7)) , 2));
+x3_M2_4 <= mularray_i(3)(6)xor std_logic_vector(shift_left(unsigned(mularray_i(3)(7)) , 3));
+x3_M2_3 <= x3_M_4 xor std_logic_vector(shift_right(unsigned(mularray_i(3)(6)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(3)(7)) , 3))) , 3));
+x3_M2_1 <= mularray_i(3)(3) xor std_logic_vector(shift_left(unsigned(mularray_i(3)(0)) , 2));
+
+mularray_o(3)(7) <= x3_M_1;
+mularray_o(3)(6) <= mularray_i(3)(1);
+mularray_o(3)(5) <= mularray_i(3)(0);
+mularray_o(3)(4) <= mularray_i(3)(7)xor std_logic_vector(shift_left(unsigned(mularray_i(3)(0)) , 3));
+mularray_o(3)(3) <= x3_M2_4 xor std_logic_vector(shift_right(unsigned(mularray_i(3)(7)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(3)(0)) , 3))) , 3));
+mularray_o(3)(2) <= x3_M2_3;
+mularray_o(3)(1) <= x3_M_3 xor std_logic_vector(shift_left(unsigned(mularray_i(3)(1)) , 2));
+mularray_o(3)(0) <= x3_M2_1;
+
+
+if_lane5_6_7: if LANE_NB>4 generate
+ mularray_o(4)(0) <= mularray_i(4)(7);
+ mularray_o(4)(1) <= mularray_i(4)(0);
+ mularray_o(4)(2) <= mularray_i(4)(1);
+ mularray_o(4)(3) <= mularray_i(4)(2) xor std_logic_vector(shift_right(unsigned(mularray_i(4)(3)), 3));
+ mularray_o(4)(4) <= mularray_i(4)(3);
+ mularray_o(4)(5) <= mularray_i(4)(4) xor std_logic_vector(shift_left(unsigned(mularray_i(4)(2)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(4)(3)) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(mularray_i(4)(5)) , 3));
+ mularray_o(4)(6) <= mularray_i(4)(5) xor std_logic_vector(shift_left(unsigned(mularray_i(4)(2)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(4)(3)) , 3) , 2));
+ mularray_o(4)(7) <= mularray_i(4)(6);
+end generate;
+
+if_lane6_7: if LANE_NB>5 generate
+ x5_MR_3 <= mularray_i(5)(2) xor std_logic_vector(shift_right(unsigned(mularray_i(5)(3)), 3));
+ x5_MR_5 <= mularray_i(5)(4) xor std_logic_vector(shift_left(unsigned(mularray_i(5)(2)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(5)(3)) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(mularray_i(5)(5)) , 3));
+ x5_MR_6 <= mularray_i(5)(5) xor std_logic_vector(shift_left(unsigned(mularray_i(5)(2)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(5)(3)) , 3) , 2));
+
+ mularray_o(5)(0) <= mularray_i(5)(6);
+ mularray_o(5)(1) <= mularray_i(5)(7);
+ mularray_o(5)(2) <= mularray_i(5)(0);
+ mularray_o(5)(3) <= mularray_i(5)(1) xor std_logic_vector(shift_right(unsigned(x5_MR_3), 3));
+ mularray_o(5)(4) <= x5_MR_3;
+ mularray_o(5)(5) <= mularray_i(5)(3) xor std_logic_vector(shift_left(unsigned(mularray_i(5)(1)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(x5_MR_3) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(x5_MR_5) , 3));
+ mularray_o(5)(6) <= x5_MR_5 xor std_logic_vector(shift_left(unsigned(mularray_i(5)(1)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(x5_MR_3) , 3) , 2));
+ mularray_o(5)(7) <= x5_MR_6;
+end generate;
+
+if_lane7: if LANE_NB>6 generate
+ x6_MR_3 <= mularray_i(6)(2) xor std_logic_vector(shift_right(unsigned(mularray_i(6)(3)), 3));
+ x6_MR_5 <= mularray_i(6)(4) xor std_logic_vector(shift_left(unsigned(mularray_i(6)(2)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(6)(3)) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(mularray_i(6)(5)) , 3));
+ x6_MR_6 <= mularray_i(6)(5) xor std_logic_vector(shift_left(unsigned(mularray_i(6)(2)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(6)(3)) , 3) , 2));
+ x6_MR2_3 <= mularray_i(6)(1) xor std_logic_vector(shift_right(unsigned(x6_MR_3), 3));
+ x6_MR2_5 <= mularray_i(6)(3) xor std_logic_vector(shift_left(unsigned(mularray_i(6)(1)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(x6_MR_3) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(x6_MR_5) , 3));
+ x6_MR2_6 <= x6_MR_5 xor std_logic_vector(shift_left(unsigned(mularray_i(6)(1)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(x6_MR_3) , 3) , 2));
+
+ mularray_o(6)(0) <= x6_MR_6;
+ mularray_o(6)(1) <= mularray_i(6)(6);
+ mularray_o(6)(2) <= mularray_i(6)(7);
+ mularray_o(6)(3) <= mularray_i(6)(0) xor std_logic_vector(shift_right(unsigned(x6_MR2_3), 3));
+ mularray_o(6)(4) <= x6_MR2_3;
+ mularray_o(6)(5) <= x6_MR_3 xor std_logic_vector(shift_left(unsigned(mularray_i(6)(0)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(x6_MR2_3) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(x6_MR2_5) , 3));
+ mularray_o(6)(6) <= x6_MR2_5 xor std_logic_vector(shift_left(unsigned(mularray_i(6)(0)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(x6_MR2_3) , 3) , 2));
+ mularray_o(6)(7) <= x6_MR2_6;
+end generate;
+
+end inv_multiplication_arch; \ No newline at end of file
diff --git a/implementations/vhdl/Decrypt/lilliputtbcii256v1/key_schedule.vhd b/implementations/vhdl/Decrypt/lilliputtbcii256v1/key_schedule.vhd
new file mode 100644
index 0000000..57079d0
--- /dev/null
+++ b/implementations/vhdl/Decrypt/lilliputtbcii256v1/key_schedule.vhd
@@ -0,0 +1,101 @@
+library IEEE;
+library work;
+use IEEE.numeric_std.ALL;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.crypt_pack.ALL;
+
+
+entity key_schedule_liliput is port
+(
+ key_i : in type_tweak_key_array;
+ round_number : in std_logic_vector(7 downto 0);
+ invert_i : in std_logic;
+ key_o : out type_tweak_key_array;
+ round_key_o : out type_key
+);
+end key_schedule_liliput;
+
+architecture key_schedule_liliput_arch of key_schedule_liliput is
+
+component multiplications port(
+ mularray_i : in type_tweak_key_array;
+ mularray_o : out type_tweak_key_array
+);
+end component;
+
+component inv_multiplication port(
+ mularray_i : in type_tweak_key_array;
+ mularray_o : out type_tweak_key_array
+);
+end component;
+
+signal key_s : type_tweak_key_array;
+signal key_s_inv : type_tweak_key_array;
+signal round_key_s : type_key;
+
+begin
+
+multiplications_t : multiplications
+port map (
+ mularray_i => key_i,
+ mularray_o => key_s
+);
+
+inv_multiplications_t : inv_multiplication
+port map (
+ mularray_i => key_i,
+ mularray_o => key_s_inv
+);
+
+key_o<=key_s when invert_i = '0' else
+ key_s_inv;
+
+if_lane4: if LANE_NB=4 generate
+ col2: for j in 0 to 3 generate
+ round_key_s(0)(j) <= key_i(0)(j) xor key_i(1)(j) xor key_i(2)(j) xor key_i(3)(j) ;
+ round_key_s(1)(j) <= key_i(0)(j+4) xor key_i(1)(j+4) xor key_i(2)(j+4) xor key_i(3)(j+4);
+ end generate;
+end generate;
+
+if_lane5: if LANE_NB=5 generate
+ col2: for j in 0 to 3 generate
+ round_key_s(0)(j) <= key_i(0)(j) xor key_i(1)(j) xor key_i(2)(j) xor key_i(3)(j) xor key_i(4)(j) ;
+ round_key_s(1)(j) <= key_i(0)(j+4) xor key_i(1)(j+4) xor key_i(2)(j+4) xor key_i(3)(j+4) xor key_i(4)(j+4);
+ end generate;
+end generate;
+
+if_lane6: if LANE_NB=6 generate
+ col2: for j in 0 to 3 generate
+ round_key_s(0)(j) <= key_i(0)(j) xor key_i(1)(j) xor key_i(2)(j) xor key_i(3)(j) xor key_i(4)(j) xor key_i(5)(j) ;
+ round_key_s(1)(j) <= key_i(0)(j+4) xor key_i(1)(j+4) xor key_i(2)(j+4) xor key_i(3)(j+4) xor key_i(4)(j+4) xor key_i(5)(j+4);
+ end generate;
+end generate;
+
+if_lane7: if LANE_NB=7 generate
+ col2: for j in 0 to 3 generate
+ round_key_s(0)(j) <= key_i(0)(j) xor key_i(1)(j) xor key_i(2)(j) xor key_i(3)(j) xor key_i(4)(j) xor key_i(5)(j) xor key_i(6)(j) ;
+ round_key_s(1)(j) <= key_i(0)(j+4) xor key_i(1)(j+4) xor key_i(2)(j+4) xor key_i(3)(j+4) xor key_i(4)(j+4) xor key_i(5)(j+4) xor key_i(6)(j+4);
+ end generate;
+end generate;
+
+
+row1: for j in 0 to 3 generate
+ round_key_o(0)(j) <= round_key_s(0)(j) xor round_number when j= 0 else --on XOR chaque element des matrices de multiplications a l'index 0 avec le numero de tour
+ round_key_s(0)(j); --on XOR chaque element des matrices de multiplications entre les index 1 et 3
+ round_key_o(1)(j) <= round_key_s(1)(j);
+end generate;
+
+
+end key_schedule_liliput_arch;
+
+
+configuration key_schedule_liliput_conf of key_schedule_liliput is
+ for key_schedule_liliput_arch
+ for multiplications_t : multiplications
+ use entity work.multiplications(Behavioral);
+ end for;
+ for inv_multiplications_t : inv_multiplication
+ use entity work.inv_multiplication(inv_multiplication_arch);
+ end for;
+ end for;
+end configuration key_schedule_liliput_conf ;
diff --git a/implementations/vhdl/Decrypt/lilliputtbcii256v1/machine_etat_chiffrement.vhd b/implementations/vhdl/Decrypt/lilliputtbcii256v1/machine_etat_chiffrement.vhd
new file mode 100644
index 0000000..2d5614c
--- /dev/null
+++ b/implementations/vhdl/Decrypt/lilliputtbcii256v1/machine_etat_chiffrement.vhd
@@ -0,0 +1,145 @@
+library IEEE;
+library work;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+use work.crypt_pack.all;
+
+entity fsm_chiffrement is port (
+ start_i : in std_logic;
+ clock_i : in std_logic;
+ reset_i : in std_logic;
+ compteur_o : out std_logic_vector(7 downto 0);
+ liliput_on_out : out std_logic; --Sortie à titre informative
+ data_out_valid_o : out std_logic; --Vient à l'entrée du round exe pour s
+ permutation_o : out std_logic;
+ invert_o : out std_logic;
+ muxsel_o : out std_logic);
+end fsm_chiffrement;
+
+architecture fsm_chiffrement_arch of fsm_chiffrement is
+
+type state is (etat_initial, initfirst,initloop,initlast,firstround, loopround, lastround);
+
+signal present, futur : state;
+signal compteur : integer range 0 to ROUND+2;
+
+
+begin
+
+compteur_o <= std_logic_vector(to_unsigned(compteur,8));
+
+process_0 : process(clock_i,reset_i,present)
+begin
+ if reset_i = '0' then
+ compteur <= 0;
+ present <= etat_initial;
+ elsif clock_i'event and clock_i='1' then
+ present <= futur;
+ if( present =loopround or present =firstround ) then
+ compteur <= compteur -1;
+ elsif ( present =initloop or present =initfirst or present =initlast ) then
+ compteur <= compteur+1;
+ else
+ compteur <= 0;
+ end if;
+ end if;
+
+end process process_0;
+
+
+process_1 : process(present, start_i,compteur)
+begin
+ case present is
+ when etat_initial =>
+ if start_i = '1' then
+ futur <= initfirst;
+ else
+ futur <= present;
+ end if;
+ when initfirst =>
+ futur <= initloop;
+ when initloop =>
+ if compteur = ROUND-1 then
+ futur <= initlast;
+ else
+ futur<=present;
+ end if;
+ when initlast =>
+ futur <= firstround;
+ when firstround =>
+ futur <= loopround;
+ when loopround =>
+ if compteur = 1 then
+ futur <= lastround;
+ else
+ futur<=present;
+ end if;
+ when lastround =>
+ futur<=etat_initial;
+ end case;
+end process process_1;
+
+process_2 : process(present)
+
+begin
+ case present is
+ when etat_initial =>
+ liliput_on_out <= '0';
+ data_out_valid_o <= '0';
+ permutation_o <= '0';
+ muxsel_o <= '1';
+ invert_o <= '0';
+
+ when initfirst =>
+ liliput_on_out <= '0';
+ data_out_valid_o <= '0';
+ permutation_o <= '0';
+ muxsel_o <= '1';
+ invert_o <= '0';
+
+ when initloop =>
+ liliput_on_out <= '0';
+ data_out_valid_o <= '0';
+ permutation_o <= '0';
+ muxsel_o <= '0';
+ invert_o <= '0';
+
+ when initlast =>
+ liliput_on_out <= '0';
+ data_out_valid_o <= '0';
+ permutation_o <= '0';
+ muxsel_o <= '0';
+ invert_o <= '0';
+
+ when firstround =>
+ liliput_on_out <= '1';
+ data_out_valid_o <= '0';
+ permutation_o <= '1';
+ muxsel_o <= '1';
+ invert_o <= '1';
+
+ when loopround =>
+ liliput_on_out <= '1';
+ data_out_valid_o <= '0';
+ permutation_o <= '1';
+ muxsel_o <= '0';
+ invert_o <= '1';
+
+ when lastround =>
+ liliput_on_out <= '1';
+ data_out_valid_o <= '1';
+ permutation_o <= '0';
+ muxsel_o <= '0';
+ invert_o <= '1';
+
+ when others =>
+ liliput_on_out <= '0';
+ data_out_valid_o <= '0';
+ permutation_o <= '0';
+ muxsel_o <= '0';
+ invert_o <= '0';
+
+ end case;
+end process process_2;
+
+end architecture fsm_chiffrement_arch; \ No newline at end of file
diff --git a/implementations/vhdl/Decrypt/lilliputtbcii256v1/multiplications.vhd b/implementations/vhdl/Decrypt/lilliputtbcii256v1/multiplications.vhd
new file mode 100644
index 0000000..0f04062
--- /dev/null
+++ b/implementations/vhdl/Decrypt/lilliputtbcii256v1/multiplications.vhd
@@ -0,0 +1,132 @@
+library IEEE;
+library work;
+use IEEE.numeric_std.ALL;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.crypt_pack.ALL;
+
+entity multiplications is
+ Port (
+ mularray_i : in type_tweak_key_array;
+ mularray_o : out type_tweak_key_array
+ );
+end multiplications;
+
+architecture Behavioral of multiplications is
+
+signal x2_M_5 : bit8;
+signal x2_M_4 : bit8;
+signal x2_M_2 : bit8;
+signal x3_M_5 : bit8;
+signal x3_M_4 : bit8;
+signal x3_M_2 : bit8;
+signal x3_M2_5 : bit8;
+signal x3_M2_4 : bit8;
+signal x3_M2_2 : bit8;
+signal x5_MR_2 : bit8;
+signal x5_MR_4 : bit8;
+signal x5_MR_5 : bit8;
+signal x6_MR_2 : bit8;
+signal x6_MR_4 : bit8;
+signal x6_MR_5 : bit8;
+signal x6_MR2_2: bit8;
+signal x6_MR2_4: bit8;
+signal x6_MR2_5: bit8;
+
+
+
+begin
+
+mularray_o(0)(7) <= mularray_i(0)(7);
+mularray_o(0)(6) <= mularray_i(0)(6);
+mularray_o(0)(5) <= mularray_i(0)(5);
+mularray_o(0)(4) <= mularray_i(0)(4);
+mularray_o(0)(3) <= mularray_i(0)(3);
+mularray_o(0)(2) <= mularray_i(0)(2);
+mularray_o(0)(1) <= mularray_i(0)(1);
+mularray_o(0)(0) <= mularray_i(0)(0);
+
+mularray_o(1)(7) <= mularray_i(1)(6);
+mularray_o(1)(6) <= mularray_i(1)(5);
+mularray_o(1)(5) <= std_logic_vector(shift_left(unsigned(mularray_i(1)(5)), 3)) xor mularray_i(1)(4);
+mularray_o(1)(4) <= std_logic_vector(shift_right(unsigned(mularray_i(1)(4)), 3)) xor mularray_i(1)(3);
+mularray_o(1)(3) <= mularray_i(1)(2);
+mularray_o(1)(2) <= std_logic_vector(shift_left(unsigned(mularray_i(1)(6)) , 2)) xor mularray_i(1)(1);
+mularray_o(1)(1) <= mularray_i(1)(0);
+mularray_o(1)(0) <= mularray_i(1)(7);
+
+x2_M_5 <= std_logic_vector(shift_left(unsigned(mularray_i(2)(5)), 3)) xor mularray_i(2)(4);
+x2_M_4 <= std_logic_vector(shift_right(unsigned(mularray_i(2)(4)), 3)) xor mularray_i(2)(3);
+x2_M_2 <= std_logic_vector(shift_left(unsigned(mularray_i(2)(6)), 2)) xor mularray_i(2)(1);
+
+mularray_o(2)(7) <= mularray_i(2)(5);
+mularray_o(2)(6) <= x2_M_5;
+mularray_o(2)(5) <= std_logic_vector(shift_left(unsigned(x2_M_5), 3)) xor x2_M_4;
+mularray_o(2)(4) <= std_logic_vector(shift_right(unsigned(x2_M_4), 3)) xor mularray_i(2)(2);
+mularray_o(2)(3) <= x2_M_2;
+mularray_o(2)(2) <= std_logic_vector(shift_left(unsigned(mularray_i(2)(5)), 2)) xor mularray_i(2)(0);
+mularray_o(2)(1) <= mularray_i(2)(7);
+mularray_o(2)(0) <= mularray_i(2)(6);
+
+x3_M_5 <= std_logic_vector(shift_left(unsigned(mularray_i(3)(5)), 3)) xor mularray_i(3)(4);
+x3_M_4 <= std_logic_vector(shift_right(unsigned(mularray_i(3)(4)), 3)) xor mularray_i(3)(3);
+x3_M_2 <= std_logic_vector(shift_left(unsigned(mularray_i(3)(6)), 2)) xor mularray_i(3)(1);
+x3_M2_5 <= std_logic_vector(shift_left(unsigned(x3_M_5), 3)) xor x3_M_4;
+x3_M2_4 <= std_logic_vector(shift_right(unsigned(x3_M_4), 3)) xor mularray_i(3)(2);
+x3_M2_2 <= std_logic_vector(shift_left(unsigned(mularray_i(3)(5)), 2)) xor mularray_i(3)(0);
+
+mularray_o(3)(7) <= x3_M_5;
+mularray_o(3)(6) <= x3_M2_5;
+mularray_o(3)(5) <= std_logic_vector(shift_left(unsigned(x3_M2_5) , 3)) xor x3_M2_4;
+mularray_o(3)(4) <= std_logic_vector(shift_right(unsigned(x3_M2_4), 3)) xor x3_M_2;
+mularray_o(3)(3) <= x3_M2_2;
+mularray_o(3)(2) <= std_logic_vector(shift_left(unsigned(x3_M_5) , 2)) xor mularray_i(3)(7);
+mularray_o(3)(1) <= mularray_i(3)(6);
+mularray_o(3)(0) <= mularray_i(3)(5);
+
+
+if_lane5_6_7: if LANE_NB>4 generate
+ mularray_o(4)(0) <= mularray_i(4)(1);
+ mularray_o(4)(1) <= mularray_i(4)(2);
+ mularray_o(4)(2) <= mularray_i(4)(3)xor std_logic_vector(shift_right(unsigned(mularray_i(4)(4)), 3));
+ mularray_o(4)(3) <= mularray_i(4)(4);
+ mularray_o(4)(4) <= mularray_i(4)(5) xor std_logic_vector(shift_left(unsigned(mularray_i(4)(6)) , 3));
+ mularray_o(4)(5) <= mularray_i(4)(6) xor std_logic_vector(shift_left(unsigned(mularray_i(4)(3)) , 2));
+ mularray_o(4)(6) <= mularray_i(4)(7);
+ mularray_o(4)(7) <= mularray_i(4)(0);
+end generate;
+
+if_lane6_7: if LANE_NB>5 generate
+ x5_MR_2 <= mularray_i(5)(3) xor std_logic_vector(shift_right(unsigned(mularray_i(5)(4)) , 3));
+ x5_MR_4 <= mularray_i(5)(5) xor std_logic_vector(shift_left(unsigned(mularray_i(5)(6)) , 3));
+ x5_MR_5 <= mularray_i(5)(6) xor std_logic_vector(shift_left(unsigned(mularray_i(5)(3)) , 2));
+
+ mularray_o(5)(0) <= mularray_i(5)(2);
+ mularray_o(5)(1) <= x5_MR_2;
+ mularray_o(5)(2) <= mularray_i(5)(4) xor std_logic_vector(shift_right(unsigned(x5_MR_4) , 3));
+ mularray_o(5)(3) <= x5_MR_4;
+ mularray_o(5)(4) <= x5_MR_5 xor std_logic_vector(shift_left(unsigned(mularray_i(5)(7)) , 3));
+ mularray_o(5)(5) <= mularray_i(5)(7) xor std_logic_vector(shift_left(unsigned(mularray_i(5)(4)) , 2));
+ mularray_o(5)(6) <= mularray_i(5)(0);
+ mularray_o(5)(7) <= mularray_i(5)(1);
+end generate;
+
+if_lane7: if LANE_NB>6 generate
+ x6_MR_2 <= mularray_i(6)(3) xor std_logic_vector(shift_right(unsigned(mularray_i(6)(4)) , 3));
+ x6_MR_4 <= mularray_i(6)(5) xor std_logic_vector(shift_left(unsigned(mularray_i(6)(6)) , 3));
+ x6_MR_5 <= mularray_i(6)(6) xor std_logic_vector(shift_left(unsigned(mularray_i(6)(3)) , 2));
+ x6_MR2_2 <= mularray_i(6)(4) xor std_logic_vector(shift_right(unsigned(x6_MR_4) , 3));
+ x6_MR2_4 <= x6_MR_5 xor std_logic_vector(shift_left(unsigned(mularray_i(6)(7)) , 3));
+ x6_MR2_5 <= mularray_i(6)(7) xor std_logic_vector(shift_left(unsigned(mularray_i(6)(4)) , 2));
+
+ mularray_o(6)(0) <= x6_MR_2;
+ mularray_o(6)(1) <= x6_MR2_2;
+ mularray_o(6)(2) <= x6_MR_4 xor std_logic_vector(shift_right(unsigned(x6_MR2_4) , 3));
+ mularray_o(6)(3) <= x6_MR2_4;
+ mularray_o(6)(4) <= x6_MR2_5 xor std_logic_vector(shift_left(unsigned(mularray_i(6)(0)) , 3));
+ mularray_o(6)(5) <= mularray_i(6)(0) xor std_logic_vector(shift_left(unsigned(x6_MR_4) , 2));
+ mularray_o(6)(6) <= mularray_i(6)(1);
+ mularray_o(6)(7) <= mularray_i(6)(2);
+end generate;
+
+
+end Behavioral;
diff --git a/implementations/vhdl/Decrypt/lilliputtbcii256v1/roundexe_liliput.vhd b/implementations/vhdl/Decrypt/lilliputtbcii256v1/roundexe_liliput.vhd
new file mode 100644
index 0000000..99e8433
--- /dev/null
+++ b/implementations/vhdl/Decrypt/lilliputtbcii256v1/roundexe_liliput.vhd
@@ -0,0 +1,143 @@
+library IEEE;
+library work;
+use IEEE.numeric_std.ALL;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.crypt_pack.ALL;
+
+entity roundexe_liliput is port (
+ clock_i : in std_logic;
+ reset_i : in std_logic;
+ data_i : in bit_data; --donnée d'entrée lors du premier Round
+ keyb_i : in bit_key;
+ tweak_i : in bit_tweak;
+ invert_i : in std_logic;
+ round_number_i : in std_logic_vector(7 downto 0);
+ permut_valid_i : in std_logic; --permet de savoir si on fait la permutation à la fin
+ muxsel_i : in std_logic; --En lien avec data_i permet la selection des données d'entrée au cours d'un Round
+ data_out_valid_i: in std_logic;
+ data_o : out bit_data
+ );
+end roundexe_liliput;
+
+architecture roundexe_liliput_arch of roundexe_liliput is
+
+component state_register port(
+ state_i : in type_state; -- Etat d'entrée
+ state_o : out type_state; -- Etatde sortie
+ clock_i : in std_logic; -- Permet de gérer la clock
+ reset_i : in std_logic
+ );
+end component;
+
+component state_key_register port(
+ state_key_i : in type_tweak_key_array; -- Etat d'entrée
+ state_key_o : out type_tweak_key_array; -- Etat de sortie
+ clock_i : in std_logic; -- Permet de gérer la clock
+ reset_i : in std_logic
+ );
+end component;
+
+component chiffrement port(
+ chiffrement_i : in type_state;
+ permutation_i : in std_logic;
+ round_key_i : in type_key;
+ chiffrement_o : out type_state;
+ data_out_valid_i: in std_logic;
+ data_o : out bit128
+ );
+end component;
+
+component key_schedule_liliput port (
+ key_i : in type_tweak_key_array;
+ round_number : in std_logic_vector(7 downto 0);
+ invert_i : in std_logic;
+ key_o : out type_tweak_key_array;
+ round_key_o : out type_key
+ );
+end component;
+
+
+signal data_i_s : type_state;
+signal chiffrement_o_s : type_state;
+signal mux_1_s : type_state; --Pour prendre en compte data_i ou le retour de state_register
+signal mux_2_s : type_tweak_key_array; --Récupération de la clef pour le round 0
+signal state_o_s : type_state;
+signal state_tk_o_s : type_tweak_key_array;
+signal round_key_o_s : type_key;
+signal tweak_key_i : bit_tweak_key := (others=>'0');
+signal tk_s : type_tweak_key_array;
+signal tk_o_s : type_tweak_key_array;
+signal round_key_s : type_key;
+
+begin
+
+convertion_ligne : for i in 0 to 3 generate
+ convertion_colonne : for j in 0 to 3 generate
+ data_i_s(i)(j) <= data_i((7+(8*(4*i+j)))downto((8*(4*i+j))));
+ end generate;
+end generate;
+
+--Tweak_key concatenation
+tweak_key_i (TWEAK_KEY_LEN downto 0)<= keyb_i & tweak_i;
+
+--formatting tweak_key in type_tweak_key_array
+convertion_ligne_key : for i in 0 to LANE_NB-1 generate
+ convertion_colonne_key : for j in 0 to 7 generate
+ tk_s(i)(j) <= tweak_key_i(((64*i)+(8*j)+7)downto((64*i)+(8*j)));
+ end generate;
+end generate;
+
+--Avantage on n'utilise le même mux donc pas de changement dans la machine d'état
+mux_1_s <= data_i_s when muxsel_i = '1'
+ else state_o_s;
+
+mux_2_s <= tk_s when muxsel_i = '1' and invert_i= '0' else
+ state_tk_o_s;
+
+key_schedule_t : key_schedule_liliput port map(
+ key_i => mux_2_s,
+ round_number => round_number_i,
+ invert_i => invert_i,
+ key_o => tk_o_s,
+ round_key_o => round_key_s);
+
+
+state_tk_register_t : state_key_register port map(
+ state_key_i => tk_o_s,
+ state_key_o => state_tk_o_s,
+ clock_i => clock_i,
+ reset_i => reset_i);
+
+chiffrement_t : chiffrement port map(
+ chiffrement_i => mux_1_s,
+ permutation_i => permut_valid_i,
+ round_key_i => round_key_s,
+ chiffrement_o => chiffrement_o_s,
+ data_out_valid_i => data_out_valid_i,
+ data_o => data_o);
+
+state_register_t : state_register port map(
+ state_i => chiffrement_o_s,
+ state_o => state_o_s,
+ clock_i => clock_i,
+ reset_i => reset_i);
+
+
+end roundexe_liliput_arch;
+
+configuration roundexe_liliput_conf of roundexe_liliput is
+ for roundexe_liliput_arch
+ for key_schedule_t : key_schedule_liliput
+ use entity work.key_schedule_liliput(key_schedule_liliputr_arch);
+ end for;
+ for state_tk_register_t : state_key_register
+ use entity work.state_key_register(state_key_register_arch);
+ end for;
+ for chiffrement_t : chiffrement
+ use entity work.chiffrement(chiffrement_arch);
+ end for;
+ for state_register_t : state_register
+ use entity work.state_register(state_register_arch);
+ end for;
+ end for;
+end configuration roundexe_liliput_conf; \ No newline at end of file
diff --git a/implementations/vhdl/Decrypt/lilliputtbcii256v1/sbox.vhd b/implementations/vhdl/Decrypt/lilliputtbcii256v1/sbox.vhd
new file mode 100644
index 0000000..7eee9d8
--- /dev/null
+++ b/implementations/vhdl/Decrypt/lilliputtbcii256v1/sbox.vhd
@@ -0,0 +1,82 @@
+library IEEE;
+library work;
+use IEEE.std_logic_1164.all;
+use work.crypt_pack.all;
+
+entity sbox is
+ port(
+ sbox_i : in bit8;
+ sbox_o : out bit8
+ );
+end sbox;
+
+
+
+architecture sbox_arch of sbox is
+
+component inner_sbox_a
+ port (
+ sbox_i : in std_logic_vector(3 downto 0);
+ sbox_o : out std_logic_vector(3 downto 0)
+ );
+end component;
+
+component inner_sbox_b
+ port (
+ sbox_i : in std_logic_vector(3 downto 0);
+ sbox_o : out std_logic_vector(3 downto 0)
+ );
+end component;
+
+component inner_sbox_c
+ port (
+ sbox_i : in std_logic_vector(3 downto 0);
+ sbox_o : out std_logic_vector(3 downto 0)
+ );
+end component;
+
+signal a,a1,b,b1,c : std_logic_vector(3 downto 0);
+
+begin
+
+inner_sbox_a_t : inner_sbox_a
+port map(
+ sbox_i => sbox_i(3 downto 0),
+ sbox_o => a
+);
+
+a1 <= a xor sbox_i(7 downto 4);
+
+inner_sbox_b_t : inner_sbox_b
+port map(
+ sbox_i => a1,
+ sbox_o => b
+);
+
+b1 <= b xor sbox_i(3 downto 0);
+
+inner_sbox_c_t : inner_sbox_c
+port map(
+ sbox_i => b1,
+ sbox_o => c
+);
+
+sbox_o(7 downto 4) <= c xor a1;
+sbox_o (3 downto 0) <= b1;
+
+end sbox_arch;
+
+configuration sbox_conf of sbox is
+ for sbox_arch
+ for inner_sbox_a_t : inner_sbox_a
+ use entity work.inner_sbox_a( inner_sbox_a_arch );
+ end for;
+ for inner_sbox_b_t : inner_sbox_b
+ use entity work.inner_sbox_b( inner_sbox_b_arch );
+ end for;
+ for inner_sbox_c_t : inner_sbox_c
+ use entity work.inner_sbox_c( inner_sbox_c_arch );
+ end for;
+ end for;
+end configuration sbox_conf ;
+
diff --git a/implementations/vhdl/Decrypt/lilliputtbcii256v1/state_key_register.vhd b/implementations/vhdl/Decrypt/lilliputtbcii256v1/state_key_register.vhd
new file mode 100644
index 0000000..60b9403
--- /dev/null
+++ b/implementations/vhdl/Decrypt/lilliputtbcii256v1/state_key_register.vhd
@@ -0,0 +1,26 @@
+library IEEE;
+library work;
+use IEEE.numeric_std.ALL;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.crypt_pack.ALL;
+
+entity state_key_register is
+ port(
+ state_key_i : in type_tweak_key_array; -- Etat d'entrée
+ state_key_o : out type_tweak_key_array; -- Etat de sortie
+ clock_i : in std_logic; -- Permet de gérer la clock
+ reset_i : in std_logic);
+end state_key_register;
+
+architecture state_key_register_arch of state_key_register is
+begin
+ process(reset_i, clock_i) -- On définit ici un process car les fonctions ne doivent pas se faire en même temps
+ begin
+ if(reset_i = '0') then
+ state_key_o <= (others => (others => (others => '0'))); --si rest_i est nul c'est que les valeurs de state_o sont nuls
+ elsif(clock_i'event and clock_i = '1') then -- Dans le cas d'un front descendant d'horloge state_o prend la valeur de state_i. On utilise un front descendant d'horloge pour un soucis de synchronisation avec sbox
+ state_key_o <= state_key_i;
+ end if;
+ end process;
+
+ end state_key_register_arch;
diff --git a/implementations/vhdl/Decrypt/lilliputtbcii256v1/state_register.vhd b/implementations/vhdl/Decrypt/lilliputtbcii256v1/state_register.vhd
new file mode 100644
index 0000000..cdba362
--- /dev/null
+++ b/implementations/vhdl/Decrypt/lilliputtbcii256v1/state_register.vhd
@@ -0,0 +1,30 @@
+library IEEE;
+library work;
+use IEEE.numeric_std.ALL;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.crypt_pack.ALL;
+
+entity state_register is
+ port(
+ state_i : in type_state; -- Etat d'entrée
+ state_o : out type_state; -- Etatde sortie
+ clock_i : in std_logic; -- Permet de gérer la clock
+ reset_i : in std_logic);
+end state_register;
+
+architecture state_register_arch of state_register is
+begin
+ process(reset_i, clock_i) -- On définit ici un process car les fonctions ne doivent pas se faire en même temps
+ begin
+ if(reset_i = '0') then
+ for i in 0 to 3 loop
+ for j in 0 to 3 loop
+ state_o(i)(j) <= (others => '0'); --si rest_i est nul c'est que les valeurs de state_o sont nuls
+ end loop;
+ end loop;
+ elsif(clock_i'event and clock_i = '1') then -- Dans le cas d'un front descendant d'horloge state_o prend la valeur de state_i. On utilise un front descendant d'horloge pour un soucis de synchronisation avec sbox
+ state_o <= state_i;
+ end if;
+ end process;
+
+ end state_register_arch;
diff --git a/implementations/vhdl/Decrypt/lilliputtbcii256v1/tb/top_tb.vhd b/implementations/vhdl/Decrypt/lilliputtbcii256v1/tb/top_tb.vhd
new file mode 100644
index 0000000..a2bd225
--- /dev/null
+++ b/implementations/vhdl/Decrypt/lilliputtbcii256v1/tb/top_tb.vhd
@@ -0,0 +1,95 @@
+library IEEE;
+library work;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+use work.crypt_pack.all;
+
+
+entity top_tb is
+end top_tb;
+
+architecture top_tb_arch of top_tb is
+
+component top is port (
+ start_i : in std_logic;
+ clock_i : in std_logic;
+ reset_i : in std_logic;
+ data_i : in bit128;
+ key_i : in bit_key;
+ data_o : out bit128;
+ tweak_i : in bit_tweak;
+ liliput_on_out : out std_logic
+ );
+end component;
+
+signal start_i_s, clock_i_s, reset_i_s : std_logic := '0';
+signal data_i_s : bit128;
+signal key_i_s : bit_key;
+signal tweak_i_s : bit_tweak;
+signal data_o_s : bit128;
+signal liliput_on_o_s : std_logic;
+
+begin
+DUT : top
+port map(
+ start_i => start_i_s,
+ clock_i => clock_i_s,
+ reset_i => reset_i_s,
+ data_i => data_i_s,
+ key_i => key_i_s,
+ tweak_i => tweak_i_s,
+ data_o => data_o_s,
+ liliput_on_out => liliput_on_o_s
+);
+
+
+-----------KEY128 TWEAK128----------
+--data_i_s <= X"ddb2ef63ab68a803679590e8c85888ca";
+--key_i_s <= X"0F0E0D0C0B0A09080706050403020100";
+--tweak_i_s <= X"0F0E0D0C0B0A09080706050403020100";
+----RESULT X"0F0E0D0C0B0A09080706050403020100";
+
+----------KEY128 TWEAK192----------
+--data_i_s <= X"e5ce0026af060b52c2ceb2e610a2958d";
+--key_i_s <= X"0F0E0D0C0B0A09080706050403020100";
+--tweak_i_s <= X"17161514131211100F0E0D0C0B0A09080706050403020100";
+----RESULT X"0F0E0D0C0B0A09080706050403020100";
+
+-----------KEY192 TWEAK128----------
+--data_i_s <= X"31a0db08b76a1f7c646cbe506860b103";
+--key_i_s <= X"17161514131211100F0E0D0C0B0A09080706050403020100";
+--tweak_i_s <= X"0F0E0D0C0B0A09080706050403020100";
+----RESULT X"0F0E0D0C0B0A09080706050403020100";
+
+-----------KEY192 TWEAK192----------
+--data_i_s <= X"75f7fe11677769882102d57daac1464d";
+--key_i_s <= X"17161514131211100F0E0D0C0B0A09080706050403020100";
+--tweak_i_s <= X"17161514131211100F0E0D0C0B0A09080706050403020100";
+--RESULT X"0F0E0D0C0B0A09080706050403020100";
+
+-----------KEY256 TWEAK128----------
+data_i_s <= X"4ecbf0236fbf05cefff41d9900efab8a";
+key_i_s <= X"1f1e1d1c1b1a191817161514131211100F0E0D0C0B0A09080706050403020100";
+tweak_i_s <= X"0F0E0D0C0B0A09080706050403020100";
+----RESULT X"0F0E0D0C0B0A09080706050403020100";
+
+-----------KEY256 TWEAK192----------
+--data_i_s <= X"3084f49f1927b4c090f9612718ff35d3";
+--key_i_s <= X"1f1e1d1c1b1a191817161514131211100F0E0D0C0B0A09080706050403020100";
+--tweak_i_s <= X"17161514131211100F0E0D0C0B0A09080706050403020100";
+----RESULT X"0F0E0D0C0B0A09080706050403020100";
+
+clock_i_s <= not(clock_i_s) after 100 ns;
+start_i_s <= '1';
+reset_i_s <= '0' , '1' after 100 ns;
+
+end top_tb_arch;
+
+configuration top_tb_conf of top_tb is
+ for top_tb_arch
+ for DUT : top
+ use entity work.top(top_arch);
+ --use configuration lib_sources.roundexe_arch;
+ end for;
+ end for;
+end configuration top_tb_conf;
diff --git a/implementations/vhdl/Decrypt/lilliputtbcii256v1/top.vhd b/implementations/vhdl/Decrypt/lilliputtbcii256v1/top.vhd
new file mode 100644
index 0000000..0f343e1
--- /dev/null
+++ b/implementations/vhdl/Decrypt/lilliputtbcii256v1/top.vhd
@@ -0,0 +1,102 @@
+library IEEE;
+library work;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+use work.crypt_pack.all;
+
+
+entity top is port (
+ start_i : in std_logic;
+ clock_i : in std_logic;
+ reset_i : in std_logic;
+ data_i : in bit128;
+ key_i : in bit_key;
+ data_o : out bit128;
+ tweak_i : in bit_tweak;
+ liliput_on_out : out std_logic
+ );
+
+end top;
+
+architecture top_arch of top is
+
+component roundexe_liliput port(
+ clock_i : in std_logic;
+ reset_i : in std_logic;
+ data_i : in bit128; --donnée d'entrée lors du premier Round
+ keyb_i : in bit_key;
+ tweak_i : in bit_tweak;
+ invert_i : in std_logic;
+ round_number_i : in std_logic_vector(7 downto 0);
+ permut_valid_i : in std_logic; --permet de savoir si on fait la permutation à la fin
+ muxsel_i : in std_logic; --En lien avec data_i permet la selection des données d'entrée au cours d'un Round
+ data_out_valid_i: in std_logic;
+ initroundkey_i : in std_logic;
+ data_o : out bit128
+ );
+end component;
+
+component fsm_chiffrement port (
+ start_i : in std_logic;
+ clock_i : in std_logic;
+ reset_i : in std_logic;
+ compteur_o : out std_logic_vector(7 downto 0);
+ liliput_on_out : out std_logic; --Sortie à titre informative
+ data_out_valid_o : out std_logic; --Vient à l'entrée du round exe pour s
+ initroundkey_o : out std_logic;
+ permutation_o : out std_logic;
+ invert_o : out std_logic;
+ muxsel_o : out std_logic);
+end component;
+
+signal data_out_valid_o_s : std_logic;
+signal permutation_o_s : std_logic;
+signal compteur_o_s : std_logic_vector(7 downto 0);
+signal muxsel_o_s : std_logic;
+signal initroundkey_s : std_logic;
+signal invert_s : std_logic;
+
+
+begin
+
+machine_a_etat : fsm_chiffrement port map(
+ start_i => start_i,
+ clock_i => clock_i,
+ reset_i => reset_i,
+ compteur_o => compteur_o_s,
+ liliput_on_out => liliput_on_out, --Sortie à titre informative
+ data_out_valid_o => data_out_valid_o_s, --Vient à l'entrée du round exe pour s
+ initroundkey_o => initroundkey_s,
+ permutation_o => permutation_o_s,
+ invert_o => invert_s,
+ muxsel_o => muxsel_o_s
+);
+
+
+roundexe_general : roundexe_liliput port map(
+ clock_i => clock_i,
+ reset_i => reset_i,
+ data_i => data_i,
+ keyb_i => key_i,
+ tweak_i => tweak_i,
+ invert_i => invert_s,
+ round_number_i => compteur_o_s,
+ permut_valid_i => permutation_o_s,
+ muxsel_i => muxsel_o_s,
+ data_out_valid_i => data_out_valid_o_s,
+ initroundkey_i => initroundkey_s,
+ data_o => data_o
+);
+
+end top_arch;
+
+configuration top_conf of top is
+ for top_arch
+ for machine_a_etat : fsm_chiffrement
+ use entity work.fsm_chiffrement(fsm_chiffrement_arch);
+ end for;
+ for roundexe_general : roundexe_liliput
+ use entity work.roundexe_liliput(roundexe_liliput_arch);
+ end for;
+ end for;
+end configuration top_conf;
generated by cgit v1.2.3 (git 2.39.1) at 2025-12-06 09:36:41 +0000